PC to FPGA Parallel Port InterfaceAn interfacing circuitry is needed to ensure proper communication between the computer and the FPGA. The computer parallel port works at TTL logic while the FPGA works on CMOS logic. As these two different families have to be interfaced for harmonious working, level transceivers are used. As eight bits of data is sent at a time, an octal transceiver is used for the parallel communication. 74LS641 is one such octal transceiver that allows bi-directional asynchronous communication between the two devices. The 74LS641 is an octal transceiver that is available as a 20 pin DIP IC. It operates on an optimal supply voltage of 5V. The IC has two data buses A and B thus there are eight channels. The data on the data buses move from either A to B or from B to A depending on the control exerted on the direction pin. Twelve signals were used between the computer and the FPGA. Of this, the eight data lines are bidirectional. The remaining four are unidirectional signals. The IC has a direction pin, which controls the direction of transfer. The open collector configuration of the IC makes it ideal for two way communication. Pull up resistors were used to ensure that signals are pulled up to the appropriate values so that they are properly recognized and interpreted. The maximum voltage on the parallel port pins is 5V while the highest voltage on the FPGA pins should not exceed 3.3V. As the Xilinx Spartan 3 series is powered by 3.3V, the pins of the transceiver that go to the FPGA are connected to a voltage of 3.3V through pull up resistors of 2.2kilo ohms. On the other hand, the signals from the FPGA have a maximum of 3.3V and hence the data bus on the IC that feeds the pins on the computer parallel port are pulled up to 5V. A 10 kilo ohm potentiometer is used to create a 3.3V needed for the signals on the FPGA side. 74LS641 has an open collector configuration, which means that the user can control the output voltage on the IC pins. Open collector circuits can be used to interface different families of devices that have different operating logic voltage levels. According to the open collector configuration, the output essentially acts as either an open circuit (no connection to anything) or a short circuit to ground. This is then coupled to an external pull-up resistor, which sets a high voltage to the output when the transistor is open. When any transistor connected to this resistor is closed, the output is forced to 0 volts. So the pull-up resistor need not be connected to a voltage similar to that of the chip supply (Vcc); a lower or higher voltage can be used instead. Open collector circuits are therefore sometimes used to interface different families of devices that have different operating logic voltage levels. Tags: PC Interface , Parallel Port , 74LS641 , Octal Transciever , Xilinx , |
