Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator

Parallel Port

The parallel port consists of eight data lines, four control lines, five status lines, and eight ground lines. In normal usage, the lines are controlled by the host computer software and the peripheral device following a protocol such as IEEE Standard 1284 - 1994. The protocol defines procedures for transferring data such as handshaking, returning status information, and so on. The table shows the functions of each pin of the Parallel Port.

Pin Parallel Port Signal In/Out Function
1 Write Out A low on this line indicates a Write, High indicates a Read.
2-9 Data 0-7 In-Out Data Bus. Bi-directional.
10 Interrupt In Interrupt Line. Interrupt occurs on Positive (Rising) Edge.
11 Wait In Used for handshaking. A EPP cycle can be started when low, and finished when high.
12 Spare In Spare-Not Used in EPP Handshake
13 Spare In Spare-Not Used in EPP Handshake
14 Data Strobe Out When Low, indicates Data transfer
15 Spare In Spare-Note used in EPP Handshake
16 Reset Out Reset-Active Low
17 Address Strobe Out When low, indicates Address transfer
18-25 Ground GND Ground

Parallel Port is configured in bidirectional mode. As the parallel port operates on TTL logic levels while the FPGA follows the CMOS logic, level translation has to be performed. For this all the data lines and the associated control and status signals are sent through a circuit that is designed for this purpose.

Parallel Port Pinout The Parallel Port is operated in BiDirectional mode, and EPP is emulated in software. See Software implementation for more details.

Tags: Parallel Port , PC Interface ,
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