Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator

Device Utilization Summary

Device Utilization Summary (estimated values)
Logic UtilizationUsedAvailableUtilization
Number of Slices 2890 3584 80%
Number of Slice Flip Flops 845 7168 11%
Number of 4 input LUTs 4989 7168 69%
Number of bonded IOBs 22 97 22%
Number of GCLKs 1 8 12%
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Apr 29 10:49:48 200903 Warnings (3 new, 0 filtered)5 Infos (5 new, 0 filtered)
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     


Tags: FPGA , Sobel , Device Utilization ,
Tag Cloud 74LS33 74LS641 Architecture BMP BMP Linux Canny Circuit DB25 Device Utilization Digital Image Processing Edge Detection FPGA Fedora GCC Image Manipulation Imtools JPEG Laplacian Linux Memory Modules Octal Transciever OpenGL PC Interface PNG Parallel Port Prewitt RAM Roberts Sobel Spartan 3 System Ubuntu VLSI Verilog XC3S400 Xilinx libjpeg libpng