Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator

Sobel Instance Architecture

      Sobel Architecture

P0, P1, P2, P3, P4, P6, P7 and P8 represents the eight 8bit pixel inputs to the Sobel Module. The module consists of signed subtractors, shift registers and modulus operators. The output of the final adder block will be 11 bits (10 bits for the data as the maximum value of the adder output is 4*255 and the 11th bit as the sign bit). The output data is compared to limit the value to a maximum of 255 as the output image is also composed of 8-bit wide pixels. 32 Sobel modules are used in parallel. The limitation on the number of parallel Sobel operators that can be implemented is logic resources available in the target device.

The Sobel output for one group of pixels calculated as per |Gx| + |Gy| where Gx and Gy are calculated from the formula given in here.

Sobel Module

The summary of the Sobel module showing the input output buses are shown above.

FPGA Statistics

A single Sobel operator logic consumes 149 four input lookup tables (LUT) which is 2% of the available FPGA resources.

SOBEL Project Status
Project File: sobel.ise Current State: Synthesized
Module Name: sobel
  • Errors:
No Errors
Target Device: xc3s400-4tq144
  • Warnings:
4 Warnings (0 new, 0 filtered)
Product Version: ISE, 8.1i
  • Updated:
Sat Feb 28 16:13:45 2009
Device Utilization Summary (estimated values)
Logic UtilizationUsedAvailableUtilization
Number of Slices 83 3584 2%
Number of Slice Flip Flops 30 7168 0%
Number of 4 input LUTs 149 7168 2%
Number of bonded IOBs 74 97 76%
Number of GCLKs 1 8 12%
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Feb 27 20:56:01 200904 Warnings (0 new, 0 filtered)0
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     



Tags: Sobel , FPGA , Architecture , Device Utilization ,
Tag Cloud 74LS33 74LS641 Architecture BMP BMP Linux Canny Circuit DB25 Device Utilization Digital Image Processing Edge Detection FPGA Fedora GCC Image Manipulation Imtools JPEG Laplacian Linux Memory Modules Octal Transciever OpenGL PC Interface PNG Parallel Port Prewitt RAM Roberts Sobel Spartan 3 System Ubuntu VLSI Verilog XC3S400 Xilinx libjpeg libpng