Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator

System Overview

The project essentially consists of manipulating images in order to perform the Sobel Edge detection algorithm. The image of selected formats like .JPEG, .PNG and .BMP are converted to the raw image data using a C program. The image was represented as pixels of 8bits (values ranging from 0 to 255). Once the computer performs the image extraction, the information thus obtained is to be sent to the FPGA in order to perform the mathematical computations. The communication between the computer and the FPGA is done via the parallel port which is operating in bidirectional mode. Appropriate handshake signals are used to eliminate errors in data transfer. As the parallel port operates on TTL logic levels while the FPGA follows the LVCMOS (3.3V), level translation has to be performed. 74LS641 which is an octal bidirectional buffer with open collector I/O was used for the level translation. The Sobel operator is applied on the block of pixels received in the memory. The processed data is transferred to the computer using the parallel port. The data thus received is further manipulated to reconstruct and display the edge detected image.

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PC to FPGA Parallel Port Interface

An interfacing circuitry is needed to ensure proper communication between the computer and the FPGA. The computer parallel port works at TTL logic while the FPGA works on CMOS logic. As these two different families have to be interfaced for harmonious working, level transceivers are used.
As eight bits of data is sent at a time, an octal transceiver is used for the parallel communication. 74LS641 is one such octal transceiver that allows bi-directional asynchronous communication between the two devices.
The 74LS641 is an octal transceiver that is available as a 20 pin DIP IC. It operates on an optimal supply voltage of 5V. The IC has two data buses A and B thus there are eight channels. The data on the data buses move from either A to B or from B to A depending on the control exerted on the direction pin. Twelve signals were used between the computer and the FPGA. Of this, the eight data lines are bidirectional. The remaining four are unidirectional signals. The IC has a direction pin, which controls the direction of transfer. The open collector configuration of the IC makes it ideal for two way communication. Pull up resistors were used to ensure that signals are pulled up to the appropriate values so that they are properly recognized and interpreted. The maximum voltage on the parallel port pins is 5V while the highest voltage on the FPGA pins should not exceed 3.3V. As the Xilinx Spartan 3 series is powered by 3.3V, the pins of the transceiver that go to the FPGA are connected to a voltage of 3.3V through pull up resistors of 2.2kilo ohms. On the other hand, the signals from the FPGA have a maximum of 3.3V and hence the data bus on the IC that feeds the pins on the computer parallel port are pulled up to 5V. A 10 kilo ohm potentiometer is used to create a 3.3V needed for the signals on the FPGA side. 74LS641 has an open collector configuration, which means that the user can control the output voltage on the IC pins. Open collector circuits can be used to interface different families of devices that have different operating logic voltage levels. According to the open collector configuration, the output essentially acts as either an open circuit (no connection to anything) or a short circuit to ground. This is then coupled to an external pull-up resistor, which sets a high voltage to the output when the transistor is open. When any transistor connected to this resistor is closed, the output is forced to 0 volts. So the pull-up resistor need not be connected to a voltage similar to that of the chip supply (Vcc); a lower or higher voltage can be used instead. Open collector circuits are therefore sometimes used to interface different families of devices that have different operating logic voltage levels.

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Parallel Port

The parallel port consists of eight data lines, four control lines, five status lines, and eight ground lines. In normal usage, the lines are controlled by the host computer software and the peripheral device following a protocol such as IEEE Standard 1284 - 1994. The protocol defines procedures for transferring data such as handshaking, returning status information, and so on. The table shows the functions of each pin of the Parallel Port.
Pin Parallel Port Signal In/Out
Function 1
Write Out
A low on this line indicates a Write, High indicates a Read. 2-9
Data 0-7 In-Out Data Bus. Bi-directional.
10 Interrupt
In Interrupt Line. Interrupt occurs on Positive (Rising) Edge.
11 Wait
In Used for handshaking. A EPP cycle can be started when low, and finished when high.
12 Spare In
Spare-Not Used in EPP Handshake 13
Spare In
Spare-Not Used in EPP Handshake 14
Data Strobe Out When Low, indicates Data transfer
15 Spare
In Spare-Note used in EPP Handshake
16 Reset
Out Reset-Active Low
17 Address Strobe Out
When low, indicates Address transfer 18-25 Ground
GND Ground
Parallel Port is configured in bidirectional mode. As the parallel port operates on TTL logic levels while the FPGA follows the CMOS logic, level translation has to be performed. For this all the data lines and the associated control and status signals are sent through a circuit that is designed for this purpose.
The Parallel Port is operated in BiDirectional mode, and EPP is emulated in software. See Software implementation for more details.

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