Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator


The aim of this project is to implement the Sobel Edge detection Operator on Hardware (Field Programmable Gate Array). The project is done as the 8th semester final Main Project in Model Engineering College, Thrikkakara under Cochin University of Science and Technology (CUSAT).

The people who are into this project are
  • Aleena Emmanuel
  • Arun Prabhakar
  • Manu Thomas Mathew
  • Sunju John
  • Vilas G. Kumar
Our Guide : Mr. Cejo K. L.
Project Coordinator : Prof. Vinu Thomas


The implementation of image edge detection on hardware is important for increasing processing speed of image processing systems. The project implements edge detection using Sobel Operator on a Field Programmable Gate Array device. Edge information for a particular pixel is obtained by exploring the brightness of pixels in the neighbourhood of that pixel. Measuring the relative brightness of pixels in a neighbourhood is mathematically analogous to calculating the derivative of brightness. The pixel information extracted is transferred from the computer to the field programmable gate array device. Sobel edge detection operations are performed on the data and the processed data is sent back to the computer. The transfer of data is done using parallel port interface operating in bidirectional mode. All the digital logic implemented and verified on the field programmable gate array kit was described using the Verilog® Hardware Description Language and the target was Xilinx Spartan 3 Family device XC3S400. The functional verification and simulation was performed using free and open source electronic design automation tools, GPLCver for Verilog compilation and GTKWave for post processing of simulation results. Conversion of image to raw format and creating the output image is done using software written in C. Xilinx Integrated Software Environment suites of tools were employed for synthesis, mapping, placement and route and for configuring the target device.