Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator

74LS641 Transciever Interface Circuit

Interface Circuit FPGA


IC1  74LS641
IC2  74LS641
IC3  74LS33
C1  DB25 connector
R  2.2K?
74LS641 is an octal transciever for converting 5 to 3.3v and back.
74LS33 is a 3.3 Voltage Regulator.
DB25 is the parallel port male connector to attach to the Parallel Port.
2.2k Resistors are pull up resistors.

Tags: PC Interface , Circuit , 74LS641 , 74LS33 , DB25 ,
Tag Cloud 74LS33 74LS641 Architecture BMP BMP Linux Canny Circuit DB25 Device Utilization Digital Image Processing Edge Detection FPGA Fedora GCC Image Manipulation Imtools JPEG Laplacian Linux Memory Modules Octal Transciever OpenGL PC Interface PNG Parallel Port Prewitt RAM Roberts Sobel Spartan 3 System Ubuntu VLSI Verilog XC3S400 Xilinx libjpeg libpng