Edge Detection in FPGA using Sobel Operator
Edge Detection in FPGA using Sobel Operator

Sobel Instance Architecture


P0, P1, P2, P3, P4, P6, P7 and P8 represents the eight 8bit pixel inputs to the Sobel Module. The module consists of signed subtractors, shift registers and modulus operators. The output of the final adder block will be 11 bits (10 bits for the data as the maximum value of the adder output is 4*255 and the 11th bit as the sign bit). The output data is compared to limit the value to a maximum of 255 as the output image is also composed of 8-bit wide pixels. 32 Sobel modules are used in parallel. The limitation on the number of parallel Sobel operators that can be implemented is logic resources available in the target device. The Sobel output for one group of pixels calculated as per |Gx| + |Gy| where Gx and Gy are calculated from the formula given in here. The summary of the Sobel module showing the input output buses are shown above.
FPGA Statistics A single Sobel operator logic consumes 149 four input lookup tables (LUT) which is 2% of the available FPGA resources.
SOBEL Project Status
Project File: sobel.ise Current State: Synthesized
Module Name: sobel Errors: No Errors
Target Device: xc3s400-4tq144 Warnings:
4 Warnings (0 new, 0 filtered)
Product Version: ISE, 8.1i Updated: Sat Feb 28 16:13:45 2009
Device Utilization Summary (estimated values)
Logic UtilizationUsedAvailableUtilization Number of Slices 83 3584 2%
Number of Slice Flip Flops
30 7168 0%
Number of 4 input LUTs 149 7168 2%
Number of bonded IOBs
74 97 76%
Number of GCLKs 1 8 12%
Detailed Reports Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentFri Feb 27 20:56:01 200904 Warnings (0 new, 0 filtered)0
Translation Report Map Report Place and Route Report Static Timing Report Bitgen Report
Sources sobelcode.v

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Edge Detection Hardware Architecture


The Block gives the overall I/O ports on the edge detection system using fpga.

The bus_rw controls the direction of data transfer while data_strobe and mode_strobe signals control the entire data transfer operation. The clk signal is the internal clock of the FPGA. The bus(7:0) is an 8 bit bidirectional data bus. Internally the system consists of Ram Modules wired to 32 FPGA modules. There are 3 sets of 34byte RAM array which can be serially loaded and parallely shifted. The 3 sets of RAM Array are wired to 32 Sobel Instances

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System Architecture


The data received from the computer is stored in three 8X34 RAM memory. In order to exploit the parallel processing capability of the FPGA, 32 parallel Sobel operators are implemented on the FPGA. The output of the Sobel operators are multiplexed and transferred to the computer.

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