Three RAM modules each of size 3X34 are employed for storing the data from computer. The contents of the RAM modules are reset before initiating computation. When the control signals ‘ready’ and ‘read_write’ are both asserted LOW, firstly the RAM module in the third row is loaded with 34 bytes of pixel values transferred from the computer via the parallel port. At the end of first data transfer operation, the contents of the RAM modules will be as follows:
Then the ‘mode_strobe’ is asserted low after placing a value of 0110_0110 in the data bus. Then the entire rows are shifted one upwards. Then the third row is filled with next set of data values. Then the RAM module will be as shown in figure 5.3
Similarly after the third data transfer, the RAM will be as shown in figure 5.4 We start the edge detection operation as the entire RAM is ready. Consecutive three elements of each row will be the input to each of the 32 Sobel Modules. Once the entire RAM is filled with valid data, only single shift need to be done to get the next set of valid data.
Tags: RAM , Modules , Memory , FPGA ,